@Article{rettberg:monarch,
  author = {Randall D. Rettberg and William R. Crowther and Philip P. Carvey
  and Raymond S. Tomlinson},
  title = {The {Monarch Parallel Processor} Hardware Design},
  journal = {IEEE Computer},
  year = {1990},
  month = {April},
  volume = {23},
  number = {4},
  pages = {18--30},
  publisher = {IEEE Computer Society Press},
  keywords = {MIMD, parallel architecture, shared memory, parallel I/O,
  pario-bib},
  comment = {This describes the Monarch computer from BBN. It was never built.
  65K processors and memory modules. 65GB RAM. Bfly-style switch in dance-hall
  layout. Switch is synchronous; one switch time is a {\em frame} (one
  microsecond, equal to 3 processor cycles) and all processors may reference
  memory in one frame time. Local I-cache only. Contention reduces full
  bandwidth by 16 percent. Full 64-bit machine. Custom VLSI. Each memory
  location has 8 tag bits. One allows for a location to be locked by a
  processor. Thus, any FetchAndOp or full/empty model can be supported. I/O is
  done by adding I/O processors (up to 2K in a 65K-proc machine) in the switch.
  They plan 200 disks, each with an I/O processor, for 65K nodes. They would
  spread each block over 9 disks, including one for parity (essentially RAID).}
}