@InProceedings{asthana:active,
  author = {Abhaya Asthana and Mark Cravatts and Paul Krzyzanowski},
  title = {An Experimental Active Memory Based {I/O} Subsystem},
  booktitle = {Proceedings of the IPPS~'94 Workshop on Input/Output in Parallel
  Computer Systems},
  year = {1994},
  month = {April},
  pages = {73--84},
  organization = {AT\&T Bell Labs},
  note = {Also appeared in Computer Architecture News 22(4)},
  later = {asthana:active-book},
  keywords = {parallel I/O, architecture, pario-bib},
  comment = {They describe an I/O subsystem based on an ``active memory''
  called SWIM (Structured Wafer-based Intelligent Memory). SWIM chips are RAM
  chips with some built-in processing. The idea is that these tiny processors
  can manipulate the data in the chip at full speed, without dealing with
  memory bus or off-chip costs. Further, the chips can work in parallel. They
  demonstrate how they've used this to build a national phone database server,
  a high-performance IP router, and a call-screening agent.}
}